1. Field of the Invention
The present invention relates to a semiconductor apparatus and a fabrication method thereof, and more particularly, to a small CMOS image sensor of high performance.
A CMOS image sensor is a kind of useful solid imaging devices. Compared with a CCD image sensor that is highly sensitive and of high image quality, a CMOS image sensor is characterized in that it can be driven with a single driving voltage and that its power consumption is about 1/10 times as large as that of a CCD image sensor. A CMOS image sensor is used for a cellar phone and a handy terminal because of these advantages.
2. Description of the Related Art
In the case of a CMOS image sensor, an imaging element and a signal processing circuit can be formed on the same semiconductor substrate and additionally, the CMOS image sensor can be fabricated in a process in which a semiconductor integrated circuit is fabricated, which is a great advantage of the CMOS image sensor.
FIG. 1 is a block diagram showing the construction of a CMOS image sensor.
As showed in FIG. 1, the CMOS image sensor 200 is constructed by the following: a photo controls the photo detecting unit 201, a reading circuit 203 that reads an amount of light the photo detecting unit 201 detects and converts the amount of light into a digital signal, and so forth. The photo detecting unit 201 is constructed by a large number of pixel cells that is arranged in a matrix such as CIF (common Intermediate Format, 352×288 pixels) and VGA (Video Graphics Array, 640×480 pixels) so that the resolution fits that of a TV telephone and a PC. An image formed on the photo detecting unit 201 is divided into the pixels, and the amount of light on each pixel is converted into a voltage signal.
FIG. 2 is a circuit diagram showing the equivalent circuit of a pixel cell.
As showed in FIG. 2, a pixel cell is constructed by a photo diode 211 that receives a light, generates electricity proportional to the amount of received light by photoelectric conversion, and stores it therein, and three n-channel MOS transistors 212-214 that reads the stored electricity as a voltage signal. The operation of the pixel cell will be described in detail.
In response to a reset signal input to the reset transistor 212, the reset transistor 212 turns on and sets the cathode of the photo diode 211 at a reset voltage (=power supply voltage VM). Electron proportional to the amount of received light is stored in the cathode so that the voltage level of the cathode lowers. In response to a select signal, the select transistor 214 is turned on, and the voltage level of the cathode of the photo diode 211 is output to a reading circuit 203 showed in FIG. 1 through the detect transistor 213 and the select transistor 214.
Subject that the number of electrons generated by the photoelectric effect is equal, the smaller the sum of the junction capacitance of the photo diode 211 and the gate capacitance of the detecting transistor 213 is, the larger the voltage level of the cathode of the photo diode 211 changes. Accordingly, the smaller the junction capacitance of the photo diode 211 and the gate capacitance of the detecting transistor 213 are, the larger the sensitivity to the amount of received light is.
On the other hand, a down-sized CMOS image sensor having even higher resolution and better image quality is desired. To achieve these objects the size of each pixel cell and a driving circuit needs to be reduced.
The scaling rule that simply applies a process of finer rule, however, does not solve the problem completely. If the gate length of a CMOS transistor is reduced in compliance with the scaling rule, the thickness of gate dielectrics needs to be reduced at the same time. For example, the process of 0.35 μm long gate demands a 7-8 nm thick dielectrics; the process of 0.25 μm long gate demands about 5 nm dielectrics; and the process of 0.18 μm long gate demands an about 3 nm thick dielectrics.
The application of a finer rule may involve various problems as discussed below.
If the thickness of gate dielectrics is reduced, a gate leaking current generally increases. Since the gate electrode of the detecting transistor 213 showed in FIG. 2 is connected to the cathode of the photo diode 211, if the gate leaking current of the detecting transistor 213 increases, the gate leaking current damages signal charge accumulated at the cathode. Especially, the gate leaking current increases in the case of a process of less than 0.25 μm in which the thickness of the gate dielectrics becomes 5-2.5 nm. The increased gate leaking current disturbs the true signal generated by photoelectric effect and decreases S/N ratio. Especially when an image is captured in a dim light, the true signal is weak, and the gate leaking current generates a white dot in the dim image and substantially degrades image quality.
If the thickness of the gate dielectrics is reduced, the gate capacitance of the detecting transistor 213 is increased. Because the detecting transistor 213 is connected to the cathode of the photo diode 211, the sum of the junction capacitance of the photo diode 211 and the gate capacitance of the detecting transistor 213 is increased. As described above, the voltage change caused by the signal charge generated by photoelectric effect is reduced, and the sensitivity of the CMOS image sensor to the amount of light is reduced.
It is desired that the cathode of the photo diode 211 be reset by a reset signal of a higher voltage level so as to avoid the effect of dispersion in the reset voltage of each reset transistor. However, the higher the level of the reset signal is, the more the gate leaking current of the reset transistor 212 increases. When the thickness of the gate dielectrics becomes 5 nm or less, the gate leaking current increases and the reliability of the gate dielectrics is degraded.
In a fine rule process, the lightly doped drain (LDD) or the source/drain region is generally formed by a dense shallow As ion layer. Because a substrate of a high impurity density is used, the junction capacitance of depletion layer formed between the source/drain region and the substrate. Consequently, the time required reading a signal voltage by charging and discharging this junction is increased, that is, reading speed is reduced. Especially, in the process of 0.25-0.18 μm rule gate length, a pocket region is often formed under the LDD or the source/drain so as to prevent the depletion layer from extending. Because the pocket is formed by an impurity region of the same conductivity type as the substrate and a high density, the junction capacity is further increased by the depletion layer formed between the source/drain region and the pocket region, and the speed of reading the signal voltage is further reduced.